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June 2007
HY[B/I]39S512400A[E/T] HY[B/I]39S512800A[E/T] HY[B/I]39S512160A[E/T]
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512-Mbit Synchronous DRAM SDRAM RoHS Compliant Products
Internet Data Sheet
Rev. 1.52
Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM
HY[B/I]39S512400A[E/T], HY[B/I]39S512800A[E/T], HY[B/I]39S512160A[E/T] Revision History: 2007-06, Rev. 1.52 Page All 13 www..com 13 15 19 21 Subjects (major changes since last revision) Adapted internet edition Corrected operation command "Power Down / Clock suspend ..." in truth table Corrected operation command "Power Down Exit" to X (WE#) Corrected text to "After the mode register is set a NOP command is required" , chapter 3.3 Corrected text to "One clock delay is required for mode entry and exit", chapter 3.5 Corrected the line "Input Capacitances: CK" in table 10, chapter 4 Qimonda template Previous Revision: 2007-05, Rev. 1.5 All Added more product types Previous Revision: 2006-01, Rev. 1.4
Previous Revision: 2007-06, Rev. 1.51
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 03292006-6Y91-0T2Z
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HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM
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w w w
Overview
D a t a S Featuresh e e t 4 U . c o m
This chapter lists all main features of the product family HY[I/B]39S512[40/80/16]0A[E/T] and the ordering information.
1.1.
* * * * * * * * * *
Fully Synchronous to Positive Clock Edge 0 to 70 C Operating Temperature for HYB... -40 to 85 C Operating Temperature for HYI... Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2 & 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 and full page Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Command Data Mask for Read / Write control (x4, x8, x16)
* * * * * * * * *
Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 8192 refresh cycles / 64 ms (7.8 s) Random Column Address every CLK (1-N Rule) Single 3.3 V 0.3 V Power Supply LVTTL Interface Plastic Package : P(G)-TSOPII-54 RoHS compliant product
TABLE 1
Performance
Product Type Speed Code Speed Grade Max. Clock Frequency @CL3 -7.5 PC133-333
1)
Unit -- MHz ns ns ns ns
@CL2
1) Max. Frequency CL/tRCD / tRP
fCK3 tCK3 tAC3 tCK2 tAC2
133 7.5 5.4 10 6
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1.2
Description
The HY[I/B]39S512[40/80/16]0A[E/T] are four bank Synchronous DRAM's organized as 4 banks x 32MBit x4, 4 banks x 16MBit x8 and 4 banks x 8Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with Qimonda advanced 0.14 m 512-MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and www..com mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V 0.3 V power supply. All 512-Mbit components are available in P(G)-TSOPII-54 packages.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type HYB39S512400AT-7.5 HYB39S512800AT-7.5 HYB39S512160AT-7.5 HYB39S512400AE-7.5 HYB39S512800AE-7.5 HYB39S512160AE-7.5 Industrial Operating Temperature (-40 C - +85 C) HYI39S512400AT-7.5 HYI39S512800AT-7.5 HYI39S512160AT-7.5 HYI39S512400AE-7.5 HYI39S512800AE-7.5 HYI39S512160AE-7.5 PC133-333-520 133MHz 4B x 32M x 4 SDRAM 133MHz 4B x 16M x 8 SDRAM 133MHz 4B x 8M x 16 SDRAM 133MHz 4B x 32M x 4 SDRAM 133MHz 4B x 16M x 8 SDRAM 133MHz 4B x 8M x 16 SDRAM PG-TSOPII-54
1)
Speed Grade PC133-333-520
Description 133MHz 4B x 32M x 4 SDRAM 133MHz 4B x 16M x 8 SDRAM 133MHz 4B x 8M x 16 SDRAM 133MHz 4B x 32M x 4 SDRAM 133MHz 4B x 16M x 8 SDRAM 133MHz 4B x 8M x 16 SDRAM
Package P-TSOPII-54
Note
Standard Operating Temperature (0 C - +70 C)
PG-TSOPII-54
1)
P-TSOPII-54
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Configuration
Pin Configuration
This chapter contains the pin configuration table and the TSOP package drawing.
2.1
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 3
Ball Configuration of the SDRAM
Ball No. Name Pin Type I I I I I I I I I I I I I I I I I I I I I Buffer Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL Address Signal 9:0, Address Signal 10/Auto precharge Chip Select Bank Address Signals 1:0 Function
Clock Signals x4/ x8/ x16 Organization 38 37 18 17 16 19 20 21 23 24 25 26 29 30 31 32 33 34 22 35 36 CLK CKE RAS CAS WE CS BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Clock Signal CLK Clock Enable Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
Control Signals x4/ x8/ x16 Organization
Address Signals x4/ x8/ x16 Organization
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HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM
Ball No.
Name
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PWR PWR
Buffer Type LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL -- --
Function
Data Signals x4 Organization 5 11
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DQ0 DQ1 DQ2 DQ3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM UDQM LDQM
Data Signal Bus [3:0]
44 50 2 5 8 11 44 47 50 53 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 39 39 15
Data Signals x8 Organization Data Signal Bus [7:0]
Data Signals x16 Organization Data Signal Bus [15:0]
Data Mask x4 / x8 Organization Data Mask Data Mask Upper Byte Data Mask Lower Byte Power Supply Power Supply Data Mask x16 Organization
Power Supplies x4 /x8/ x16 Organization 3, 43, 49 VDDQ 1, 14
VDD
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Ball No.
Name
Pin Type PWR PWR
Buffer Type -- --
Function Power Supply Ground for DQs Power Supply Ground
6, 12, 46, VSSQ 52 28, 41, 54
VSS
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2, 4, 7, 8, NC 10, 13, 15, 40, 42, 45, 47, 48, 51, 53 4, 7, 10, 13, 15, 40, 42, 45, 48, 51 40 NC
NC
--
Not connected
Not connected x8 Organization NC -- Not connected
Not connected x16 Organization NC NC -- Not connected
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HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM
FIGURE 1
Ball Configuration P(G)-TSOPII-54
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Functional Description
TABLE 4
Truth Table: Operation Command
Device State Idle3) Any Any Active3) Active
3)
This chapter lists all defined commands and their usage for this Synchronous DRAM family.
Operation Bank Active Bank Precharge Precharge All Write Write with Auto precharge Read Read with Auto precharge Mode Register Set No Operation Burst Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Power Down/ Clock Suspend Entry Power Down/ Clock Suspend Exit Data Write/ Output Enable Data Write/ Output Disable
CKE n-11)2) H H H H H H H H H H H H H L H L H H
CKE n1)2) X X X X X X X X X X X H L H L H X X
DQM
1)2)
BA0 BA11)2) V V X V V V V V X X X X X X X X X X
AP= A101)2) V L H L H L H V X X X X X X X X X X
Addr. CS
1)2) 1)2)
RAS
1)2)
CAS WE
1)2) 1)2)
X X X X X X X X X X X X X X X X L H
V X X V V V V V X X X X X X X X X X
L L L L L L L L L L H L L H L H L H L X X
L L L H H H H L H H X L L X H X H X H X X
H H H L L L L L H H X L L X H X H X H X X
H L L L L H H L H L X H H X X X H X H X X
Active3) Active Idle Any Active Any Idle Idle Idle (Self Refr.) Active or Idle or Burst Active or Idle or Burst Active Active
3)
1) V = Valid, x = Don't Care, L = Low Level, H = High Level 2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3) This is the state of the banks designated by BA0, BA1 signals.
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TABLE 5
Mode Register Definition (BA[1:0] = 00B)
Field BL Bits [2:0] Type w Description Burst Length Number of sequential bits per DQ related to one read/write command, see Note: All other bit combinations are RESERVED 000B 001B 010B 011B 111B BT 3 w 1 2 4 8 Full Page (Sequential burst type only)
Burst Type See Table 6 for internal address sequence of low order address bits. Sequential 0B Interleaved 1B CAS Latency Number of full clocks from read command to first data valid window. Note: All other bit combinations are RESERVED. 010B 2 011B 3
CL
[6:4]
w
Mode
[12:7]
w
Operation Mode Note: All other bit combinations are RESERVED. 0B 1B Burst read/burst write Burst read/single write
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HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM
TABLE 6
Burst Length and Sequence
Burst Length Starting Column Address A2 2 www..com 4 0 0 1 1 8 0 0 0 0 1 1 1 1 FullPage Notes 1. 2. 3. 4. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access with in the block. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. n 0 0 1 1 0 0 1 1 A1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Order of Accesses Within a Burst Type=Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 .... Type=Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported
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4.1
Electrical Characteristics
Operating Conditions
TABLE 7
Absolute Maximum Ratings
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Parameter
Symbol
Limit Values Min. Max. +4.6 +4.6 +4.6 +70 +85 +150 1 50
Unit
Note/ Test Condition -- -- -- -- -- -- -- --
Input / Output voltage relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating Temperature for HYB... Operating Temperature for HYI... Storage temperature range Power dissipation per SDRAM component Data out current (short circuit)
VIN, VOUT VDD VDDQ TA TA TSTG PD IOUT
-1.0 -1.0 -1.0 0 -40 -55 -- --
V V V C C C W mA
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
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TABLE 8
DC Characteristics
Parameter Symbol Values Min. Max.
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Unit Note/ Test Condition V V V V V A A
1) 1) 1)2) 1)2) 1) 1)
VDD I/O Supply Voltage VDDQ Input high voltage VIH Input low voltage VIL Output high voltage (IOUT = - 4.0 mA) VOH Output low voltage (IOUT = 4.0 mA) VOL Input leakage current, any input (0 V < VIN < VDD, all other inputs = 0 V) IIL IOL Output leakage current (DQs are disabled, 0 V < VOUT < VDDQ)
Supply Voltage
3.0 3.0 2.0 2.4 -- -5 -5
3.6 3.6
VDDQ + 0.3 V
-- 0.4 +5 +5
-0.3 +0.8
-- --
1) All voltages are referenced to VSS 2) VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
TABLE 9
Input and Output Capacitances
Parameter Symbol Values Min. Input Capacitances: CK Input Capacitance (A0-A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) Input/Output Capacitance (DQ) 1) VDD,VDDQ = 3.3 V 0.3 V, f = 1 MHz, TA see Table 7 CI1 CI2 CI0 2.5 2.5 4.0 Max. 3.5 3.8 6.0 pF pF pF
1)2) 1)2)
Unit
Note
1)2)
2) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF
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TABLE 10
IDD Conditions
Parameter Operating Current
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Symbol One bank active, Burst length = 1 Power down mode Non-power down mode Active state (max. 4 banks) Read command cycling Auto Refresh command cycling Self Refresh Mode, CKE=0.2 V, tCK=infinity
Precharge Standby Current No Operating Current Burst Operating Current Auto Refresh Current Self Refresh Current
IDD1 IDD2P IDD2N IDD3N IDD3P IDD4 IDD5 IDD6
TABLE 11
IDD Specifications and Conditions
Symbol Test Condition -7.5 Typ. Max. 145 3 31 35 4 123 300 -- 4 mA mA mA mA mA mA mA mA mA
2)3) 2) 2) 2) 2) 2)3) 4)
Unit
Note 1)
IDD1 IDD2P IDD2N IDD3N IDD3P IDD4 IDD5 IDD6
tRC = tRC(min), IO = 0 mA
CS =VIH (min.), CKE VIL(max) CS =VIH (min.), CKE VIH(min) CS = VIH(min), CKE VIH(min.) CS = VIH(min), CKE VIL(max.)
123 0.6 23 26 2 97 255 -- 2.1
tRFC= tRFC(min) tRFC= 15.6 s
-- --
1) TA = 0 to 70 C for HYB.., TA = -40 to 85 C for i-temp part (HYI..); VSS = 0 V, VDD, VDDQ = +3.3 V 0.3 V 2) These parameters depend on the cycle rate. All values are measured at 133 MHz for "-7.5" components with the outputs open. Input signals are changed once during tck . 3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded. 4) tRFC= tRFC(min) "burst refresh", tRFC= 15.6 s "distributed refresh".
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4.2
AC Characteristics
TABLE 12
AC Timing - Absolute Specifications
www..com Parameter
Symbol
-7.5 PC133-333 Min. Max. -- -- 5.4 6 -- -- 1.2 -- -- -- -- -- 7.5 -- -- 100k -- -- -- -- 64 -- -- -- 7 2
Unit
Note1)2)3)
Clock and Clock Enable Clock Frequency Access Time from Clock
tCK tAC
7.5 10 -- -- 2.5 2.5 0.3 1.5 0.8 1.5 0.8 2 0 20 20 45 67 67 15 1 - 1 3 1 3 --
ns ns ns ns ns ns ns ns ns ns ns
CL3 CL2 CL3 CL2
3)4)5)
Clock High Pulse Width Clock Low Pulse Width Transition time Setup and Hold Times Input Setup Time Input Hold Time CKE Setup Time CKE Hold Time Mode Register Set-up to Active delay Power Down Mode Entry Time Common Parameters Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Row Cycle Time during Auto Refresh Activate(a) to Activate(b) Command period CAS(a) to CAS(b) Command period Refresh Cycle Refresh Period (8192 cycles) Self Refresh Exit Time Data Out Hold Time Read Cycle Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
tCH tCL tT tIS tIH tCKS tCKH tRSC tSB tRCD tRP tRAS tRC tRFC tRRD tCCD tREF tSREX tOH tLZ tHZ tDQZ
6) 6) 6) 6)
tCK
ns ns ns ns ns ns ns
7) 7) 7) 7) 7)
tCK
ms
tCK
ns ns ns
3)5)
tCK
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HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM
Parameter
Symbol
-7.5 PC133-333 Min. Max. -- -- --
Unit
Note1)2)3)
Write Cycle Last Data Input to Precharge
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tWR tDAL(min.) tDQW
15 -- 0
ns
8)
Last Data Input to Activate (Write with Auto Precharge) DQM Write Mask Latency
tCK tCK
9)
1) TA = 0 to 70 C for HYB..., TA = -40 to 85 C for i-temp part (HYI..); VSS = 0 V, VDD, VDDQ = 3.3 V 0.3 V, tT = 1 ns 2) For proper power-up see the operation section of this data sheet. 3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V. 4) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 5) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load. 6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing period (counted in fractions as a whole number) 8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without AutoPrecharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tCK greater or equal the specified tWR value, where tck is equal to the actual system clock time. 9) When a Write command with Auto Precharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal to the actual system clock time.
FIGURE 2
Measurement conditions for tAC and tOH
t CH C LO C K 1 .4 V tCL t IH tT 2 .4 V 0 .4 V
t IS
IN P U T tA C t LZ OUTPUT
1 .4 V tA C t OH 1 .4 V t HZ
IO.vsd
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Package Outlines
FIGURE 3
Package Outline PG-TSOPII-54 (top view)
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List of Figures
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Figure 1 Figure 2 Figure 3
Ball Configuration P(G)-TSOPII-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Measurement conditions for tAC and tOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package Outline PG-TSOPII-54 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM
List of Tables
Table 1 Table 2 Table 3 www..com Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ball Configuration of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Truth Table: Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC Timing - Absolute Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM
Table of Contents
www..com
1 1.1 1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2 2.1 3 4 4.1 4.2 5
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Internet Data Sheet
www..com
Edition 2007-06 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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